1. Field of the Invention
The present invention relates to a drive system for a thin-film electroluminescent (EL) display panel, and more particularly, to an improvement of the EL panel drive sysems which can save electric power.
2. Description of the Prior Art
A thin-film EL display panel 10, such as shown in FIG. 1, includes a transparent glass plate 1 on which transparent stripe electrodes 2 are deposited parallel to each other. Then, a layer 3 made of a transparent dielectric material is deposited over the electrodes 2, and an EL layer 4 is deposited on dielectric layer 3. Another layer 5 made of a dielectric material is deposited on the EL layer 4, and stripe electrodes 6 are deposited, orthogonal to stripe electrodes 2, on dielectric layer 5. At the crossing point of two electrodes 2 and 6, the EL layer 4 generates a spot of light which can be viewed through glass plate 1. Thus, by illuminating a number of spots, an image can be produced on the EL display panel.
According to the prior art, there are two method to drive the EL panel: one method is called the field refresh driving method; and the other is called the P-N alternating method. The present invention is particularly concerned with the P-N alternating method in which writing operations for the P-ch field and N-ch field are carried out alternately.
An example of a prior art EL panel drive system employing the P-N alternating method is shown in FIG. 2, and is disclosed, for example, in U.S. patent application Ser. No. 718,239, filed Apr. 1, 1985 (a counterpart to UK patent application published Nov. 20, 1985 as GB No. 2,158,982 A) and assigned to the same assignee as the present application.
In FIG. 2, EL panel 10 includes a plurality of data electrodes Y1, Y2, . . . , and Yj, and a plurality of scan electrodes X1, X2, X3, . . . , and Xi. Every other scan electrodes with odd numbers X1, X3, . . . , and Xi-1 are connected to an odd side N-ch high voltage MOS IC 20, which includes N-type MOS transistors NT1, NT3, . . . , and NTi-1. These transistors are activated by signals from a shift register 21. Similarly, the even number scan electrodes X2, X4, . . . , and Xi are connected to an even side N-ch high voltage MOS IC 30, which includes N-type MOS transistors NT2, NT4, . . . , and NTi. These transistors are activated by signals from a shift register 31.
Also, the odd number scan electrodes X1, X3, . . . , and Xi-1 are connected to an odd side P-ch high voltage MOS IC 40, which includes P-type MOS transistors PT1, PT3, . . . , and PTi-1. These transistors are activated by signals from a shift register 41. Similarly, the even number scan electrodes X2, X4, . . . , and X1 are connected to an even side P-ch high voltage MOS IC 50, which includes P-type MOS transistors PT2, PT4, . . . , and PTi. These transistors are activated by signals from a shift register 51.
The data electrodes Y1, Y2, . . . , and Yj are connected to a data side N-ch high voltage MOS IC 60, which includes N-type MOS transistors Nt1, Nt2, . . . , and Ntj. These transistors are activated by a shift register 61. A data side diode array 70 is provided for separating the data side driving line and for preventing the application of a reverse biased voltage to the swiching transistors.
A picture element is defined at each crossing point of the scan electrode and the data electrode, which illuminates when a predetermined voltage, such as 220 volts, is applied across the scan and data electrodes. By using different combinations of illuminated dots, various characters and pictures can be produced on the EL panel.
The circuit shown in FIG. 2 further includes a precharge circuit 80, a pull-up charge circuit 90, a write-in circuit 100 and a source level switching circuit 110 which are operated in response to signals S1, S2, S31 (and/or S32) and S4 produced from a display control circuit (not shown).